Data Conversion Jitter Calculator Tool Introduction
Clock jitter is a problem because it introduces uncertainty (noise) into the data conversion process. Jitter in the time domain is equivalent to phase noise in the frequency domain. Phase noise spreads a portion of the clock signal power from the baseband to other frequencies. This is important because sampling can be equivalent to addition or multiplication in the time domain, which is equivalent to convolution in the frequency domain, so that the spectrum of the sampling clock is convolved with the spectrum of the input signal. And because jitter is broadband noise in the clock signal, it also appears as broadband noise in the sampling spectrum, which repeats periodically at the sampling rate. Broadband noise deteriorates the noise floor characteristics of the analog-to-digital converter (ADC).
What is the relationship between data converter jitter, phase noise, and signal-to-noise ratio (SNR)?
Clock jitter is a problem because it introduces uncertainty (noise) into the data conversion process. Jitter in the time domain is equivalent to phase noise in the frequency domain. Phase noise spreads a portion of the clock signal's power from the baseband to other frequencies. This is important because sampling can be equivalent to addition or multiplication in the time domain, which is equivalent to convolution in the frequency domain, so that the spectrum of the sampling clock is convolved with the spectrum of the input signal. And because jitter is broadband noise in the clock signal, it also appears as broadband noise in the sampling spectrum, which repeats periodically at the sampling rate. Broadband noise degrades the noise floor characteristics of the analog-to-digital converter (ADC).
The encoded signal is convolved with the analog input so that the clock spectrum (left) is represented on the analog signal. Since the ADC is a sampling system, the broadband noise of the sampling clock is also aliased in the additional band (right), which causes all broadband noise to enter the encoding section and mix into the Nyquist zone.
What equations can be used to analyze the effects of jitter and phase noise on a converter?
To calculate the effect of phase noise on SNR, consider that clock delay is equivalent to phase delay at a given frequency. From a noise power perspective, this means that the phase noise expressed in rms radians, σ2θ, is equal to ω2clk time, σ2τ, where στ is the phase jitter expressed in rms seconds and ωclk is the clock frequency in radians per second. Thus, for any jitter error, the higher the signal frequency, the greater the phase error. The relationship between phase noise and SNR can be defined by the following equation:
SHRCLK(dB)=-10logσ2θ
Assume a simple case where the bandwidth of the clock jitter falls into a single Nyquist zone and excludes quantization noise and thermal noise. In a single-carrier system, the SNR of the signal when acquiring data with a jittered clock signal can be expressed as:
SHRsig(dB)=1/(4π2σ2τf0)
In multi-carrier narrowband systems, the SNR expressed in decibels referenced to one of the carriers ( dBc) has the same form, but with the f0 term in the denominator replaced by the sum of all frequency terms. This is important because it raises the level of quantization noise and thermal noise, which dominate in applications where jitter may not contribute much to the overall SNR. In wideband systems, however, assuming the data has a zero mean and a flat, uniformly distributed spectrum between the two frequencies fL and fH, the SHR can be expressed as:
SHRsig=(1/σ2τ)×3/(f2H+fHfL+f2L)
What happens if the converter operates above baseband?
In sampling systems where the signal frequency occupies a higher frequency Nyquist band, the clock signal is required to have better jitter characteristics than the baseband system. This is because if the jitter is large enough, the noise caused by jitter may be mixed into the band. In such applications, the upper limit of the SNR caused by jitter can be determined by the following equation:
SNR(dB)=-20log(2πfanalogtrmsjitter)
Here fanalog is the input frequency and t is the jitter. Given the operating frequency and the required SNR, the clock jitter requirement can be determined using the following equation:
Tjitter=(10(-snr/20))/2πfanalog
Therefore, if jitter is the only limiting factor in converter performance, sampling a 70-MHz IF signal and maintaining a 75-dB SNR requires limiting the maximum clock jitter to 400 fs.
How do synchronous data converters differ from synchronizing other digital applications?
In fact, the jitter or phase noise level that can be allowed for high-speed data converters is lower than that of ultra-high-speed communication systems. For example, the Sonet/SDH specification allows clock jitter of the order of a few picoseconds. However, for a data converter operating at a sampling rate of 100M points/second and an input analog signal frequency between 70 and 200MHz, the jitter must be less than 1ps.