The issues discussed in this article involve the application of parallel MOSFETs in high-power, high-frequency switches; by debugging PCB traces and important circuit parameters, the causes of voltage and current imbalance problems on parallel drive MOSFETs circuits are studied;

Introduce

Due to its low on-resistance and fast switching characteristics, MOSFETs are widely used in switching power supplies and motor drives such as electric bicycles, electric cars, electric tools, electric lawn mowers, etc. In these high-power applications, multiple MOSFETs are usually required to be connected in parallel to improve overcurrent capability and efficiency.

Multiple factors affect the parallel performance of high-speed power MOSFETs; deviations in actual device parameters, asymmetric gate drive, and poor PCB layout can all cause problems; first, unbalanced currents in parallel MOSFETs can cause overcurrent problems, damaging one or more MOSFETs; second, the drain and source voltages applied to each MOSFET may actually be different, and the drain voltage may reach destructive levels during some period; finally, parasitic oscillations may appear at the gate of each MOSFET, causing the gate and source voltages to exceed their maximum rated VDS, Damage to one or more MOSFETs, this application note examines each problem in detail and provides recommendations and solutions;

Unbalanced Current and Voltage in Parallel MOSFET Applications

Under steady state conditions, MOSFETs connected in parallel work well, with equal voltage, current across each MOSFET, and the on-resistance (RDS(ON)) of the MOSFETs has a positive temperature coefficient, which means that RDS(ON) increases with temperature. This phenomenon helps in paralleling MOSFETs because it helps balance the current flow between multiple MOSFETs. Current flows to the path of least resistance. As the current in one MOSFET increases, the power dissipation increases, heating the device and increasing RDS(ON). At this time, the current will flow to other MOSFETs with lower resistance, resulting in the same current between MOSFETs.

Under switching conditions, the situation is quite different. At this time, the action of the MOSFET is similar to a voltage-controlled switch. During the dynamic process of switching, many factors can cause imbalances in current and voltage. Especially at high frequencies, the characteristics of the MOSFET, including gate threshold voltage, forward transconductance, total gate charge (Qg), RDS(ON), the actual drive circuit and the parasitic inductance in the PCB, will all lead to imbalance in current and voltage. MOSFET parameters are fixed when the device is produced and cannot be changed in the application. Screening MOSFET parameters to obtain an accurate match in price and performance is challenging. The best way to prevent problems is to use appropriate gate drive design techniques to ensure that the current and voltage across parallel MOSFETs maintain a proper balance.

▶Current imbalance caused by MOSFET parameters

Understanding MOSFET parameters and how they affect current, voltage balance in parallel MOSFET applications is the first step in determining the correct solution to possible problems.

Gate to Source Threshold Voltage (VGS(TH)): Parallel MOSFETs are usually driven by the same gate driver or gate drive signal. The MOSFET with lower VGS(TH) will turn on faster than the MOSFET with higher VGS(TH). This results in a higher current flowing through the MOSFET with lower VGS(TH), causing a current imbalance.

Forward transconductance (gFS): Between the cutoff region where the MOSFET is turned off and the saturation region where the MOSFET is fully turned on is the variable resistance region. The drain current is controlled by the gate-to-source voltage VGS. This region is determined by the forward transconductance gFS characteristics of the device. Different VGS will cause a current imbalance during the transition from on to off, and vice versa.

Gate charge (Qg): The total gate charge, the total gate charge required to turn on the MOSFET and make the current flow from drain to gate, will significantly affect the switching speed of the MOSFET; when multiple MOSFETs are connected in parallel, if one of the MOSFETs has a lower Q value, it will turn on faster than the other MOSFETs. This faster turn-on causes the MOSFET to handle most of the current during the transition period, resulting in another unbalanced current state.

▶The effect of gate driver impedance on current imbalance leads to another unbalanced current condition

In the gate driver circuit shown in Figure 1, a mismatch example was created and tested to show the effect of mismatched gate resistors. As shown in Section 3, it is recommended to use gate resistors in high frequency applications to avoid additional complexity. It is critical to ensure that these gate resistors are as matched as possible. In the gate drive circuit shown in Figure 1, Q1 and Q2 are connected in parallel, R1 is the drive resistor in series with the gate of Q1, and R3 is connected to the gate of R1 and Q2. This will cause the gate driver to be mismatched.

Figures 2a and 2b show VGS during turn-on and turn-off caused by gate drive resistor mismatch. Channel 1 shows Q1 turning on and off faster. This is a result of low gate resistivity. The faster switching time induces a higher current through Q1 compared to the current flowing through Q2. The higher current flowing through Q1’s drain and source parasitic inductance results in larger voltage spikes and ringing. The difference between Q1 and Q2 in Figures 2a and 2b shows that Q1 handles a greater peak current during switching due to the gate driver resistance mismatch. It is important to balance the current through each MOSFET during the switching process to avoid applying too much current to one of the MOSFETs in a parallel application. Using matched gate resistors is key to achieving the desired performance.

▶ Effect of gate drive circuit layout on voltage imbalance

In high-power, high-frequency applications, the parasitic inductance of the PCB can have a negative impact on the entire system, and if the stray inductance in the drain is not well controlled, it can cause the MOSFET to fail. Figure 3 shows the parasitic inductance in two parallel MOSFETs, intentionally skewed to simulate poor layout. In this circuit, the drain inductance of Q1 is 40nH (L1), the inductance of Q2 is 20nH (L2), and AOT470 is the 75V MOSFET selected for this simulation.

During shutdown, the voltage will be superimposed on the maximum drain voltage determined by the parasitic inductance and changing current (V=L*di/dt). If the matching circuit consists of the same di/dt characteristics and the parasitic inductance is optimized for each MOSFET, the maximum drain voltage seen by each device will be approximately the same.

When the parasitic inductance in the drain is different, the two excess voltages caused by V=L di/dt will not be equal. This difference in turn affects the magnitude of di/dt and ultimately results in a higher drain voltage on Q1. In addition, due to the large drain inductance of Q1, when L1 rings together with the Coss of the AOT470 and the parasitic resistance in the circuit, its ringing amplitude (as shown in Figure 4) is also large. This combination of ringing and voltage spikes on the drain during shutdown can easily cause the MOSFET to exceed its maximum rated drain-to-source voltage and cause failure. Circuit designers can avoid these mismatches by carefully designing the gate driver circuit as shown in Section 2.2 and minimizing parasitic circuit inductance during PCB layout.

Managing potential potential oscillations in parallel MOSFET applications

When connecting two MOSFETs in parallel, many designers prefer to connect the two gates and the two drains directly together. However, this method can easily lead to gate oscillation. In the worst case, the oscillation amplitude may even exceed the maximum rated gate voltage, ultimately damaging the MOSFET.

▶ Examples of oscillations

Figure 5 shows an example of the oscillation that can occur when two gates are connected directly together. A high frequency oscillation of ~150MHz occurs during the on and off transitions. These oscillations often have very high amplitudes and can easily exceed the maximum rating of the gate-source voltage or drain-source voltage, damaging the device.

The oscillation can be easily eliminated by using a separate gate drive resistor. Figure 6 shows the results of adding a single resistor to the gate of each MOSFET. The gate and drain voltages on both MOSFETs are nearly identical, meaning that when connected in parallel, it can be assumed that the current through each device is the same. This greatly improves the reliability of the circuit.

▶ Root cause analysis of gate oscillation

In order to understand the cause of high-frequency oscillations at the gates of two MOSFETs directly connected together, it is important to analyze the equivalent circuit. Figure 7 shows two MOSFETs in parallel with the parasitic drain inductance, gate capacitance (Cgd) and gate resistance in detail. These components form a low impedance loop and can be viewed as a series RLC equivalent circuit.

Resonant frequency of series RLC circuit:

Series RLC circuit quality factor:

Equations 1 and 2 determine the resonant frequency of the series equivalent circuit and the quality factor (Q) at that resonant frequency. The lower the impedance of the circuit, the higher the Q factor produced. The more selectively a circuit responds to signals of a specific frequency, the higher the amplitude of the oscillations produced. To avoid this oscillation, it is recommended to connect equal gate resistors in series with each gate. This will help dampen oscillations when the loop impedance is very low.

When two AOT474 power MOSFETs are connected in parallel, the resulting oscillation is due to a reduction in the C value, which in turn increases the Q factor (Q is inversely proportional to C). The solution is to connect a separate gate resistor of 10Ώ to the gate of each MOSFET to lower the Q factor and suppress oscillations on the gate, as shown in Figure 6.

The circuit simulations in Figures 8a, 8b, and 9 further demonstrate why the series gate resistor is important to suppress oscillations. The parameters used in this model are from the electrical specifications of the AOT474 data sheet. The device has an internal R of 2.8Ώ and C of 36pF. Assuming that the parasitic inductance in the loop is 60nH, the new equivalent circuit and equivalent impedance value are shown in Figure 8a. Figure 8b shows the effect of adding a 10Ώ series gate resistor to each MOSFET, increasing the effective gate resistance from 5.6Ω to 25.6Ω.

Small signal analysis using parameters obtained from the AOT474 datasheet and the equivalent circuit model shown in Figures 8a and 8b produced the results shown in Figure 9. The red curve obtained by simulating the circuit in Figure 8a shows a resonant frequency of approximately 150MHz at high Q, which corresponds well to the waveform shown in Figure 5. The blue curve is the simulation result of the equivalent circuit in Figure 8b, showing the effect of adding a 10Ω gate resistor to each MOSFET gate. The Q factor of the circuit is significantly reduced, explaining the result of the very clean gate drive waveform shown in Figure 6.

In conclusion:

When using parallel MOSFETs in switching applications, care must be taken when designing the circuit in order to obtain optimal current sharing and voltage balance. Dedicated gate resistors for each MOSFET will help match on and off times while eliminating the possibility of high frequency oscillation. During the PCB layout process, proper attention is paid to minimizing current loops while keeping trace lengths short, wide, and matched to reduce the amount of parasitic inductance in high current paths. This will help keep voltages equal and within design specifications.